In a high speed synchronous semiconductor memory device, such as a double data rate synchronous dynamic random access memory (“DDR SDRAM”), data is transferred to other devices, where the data is synchronized with a clock signal (e.g., a reference clock or an external clock signal). The high speed synchronous semiconductor memory device performs an input or output operation in synchronization with not only a rising edge, but also a falling edge of the clock signal. Typically, in a system or a circuit including a semiconductor memory, the clock signal is used as a reference clock signal for adjusting operation timing to guarantee stable data access and data transfer without error. For stable data access and data transfer, a delay occurring from processing and receiving the data can be compensated for during the data transfer by exactly setting the data transfer at edges of the clock signal or at centers of the clock signal.
Various components of the semiconductor memory device may need a clean copy of the reference clock signal with a predefined phase delay. Thus, a delay locked loop (“DLL”) can generate internal clock signals for the system based upon the reference clock signal by compensating for clock skew occurring in the data path and adding phase delays to the reference clock signal. The data path has a predetermined delay amount estimated from the clock skew, where the data or the clock signal passes through the semiconductor memory device. The generated internal clock signals can then be used for synchronizing data input/output.
DLLs can be used to supply these internal clock signals based on the reference clock signal. Typically, DLLs are based on a variable multi-stage delay line, in which the delay is controlled by a phase/frequency detector which compares the signal at the end of the delay line with the reference clock signal. Taps between stages in the delay line provide multiple copies of the reference signal, phase shifted so as to subdivide the clock period into different phase delay levels.
A DLL can provide delays in steps up to a full clock cycle delay for the input signal. Typically, the DLL can have eight delay segments (also referred to as octants) that are connected in series to provide total delay up to one clock period. Each of the DLLs can provide delay around ⅛th of the clock cycle. The actual delay can be less or more than ⅛th of the clock period due to PVT variations. Since the delays are provided by active elements that work in a feedback loop, these elements need to be calibrated against different phases of the reference clock signal e.g., 45 degrees, 90 degrees, 135 degrees, . . . and 315 degrees. However, this is not only costly to generate the reference phases, but imposes routing restrictions to bring these phases to the DLL and to other DLLs of the system for calibration of those DLLs.
Current techniques for calibrating the DLL are to route one or more reference clocks to all the DLLs of the memory system. However, the memory system is quite expansive and would require a great amount of resources to route reference clocks to all of the DLLs of the memory system. Therefore, it is desirable to provide new methods and systems for calibrating a DLL to account for PVT variations.